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CY7C199
32K x 8 Static RAM
Features
* High speed -- 10 ns * Fast tDOE * CMOS for optimum speed/power * Low active power -- 467 mW (max, 12 ns "L" version) * Low standby power -- 0.275 mW (max, "L" version) * 2V data retention ("L" version only) * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers. This device has an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the standard 300-mil-wide DIP, SOJ, and LCC packages. An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and Write Enable (WE) is HIGH. A die coat is used to improve alpha immunity.
Functional Description
The CY7C199 is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14
22 23 24 25 26 27 28 1 2 3 4 5 6 7
LCC Top View
3 2 1 28 27 4 26 A4 5 25 A3 6 24 A2 7 23 A1 8 22 OE 9 21 A0 20 CE 10 11 19 I/O7 18 I/O6 12 1314151617 I/O2 GND I/O3 I/O4 I/O5 A7 A6 A5 VCC WE A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1
I/O0
INPUT BUFFER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
CE WE OE
I/O1
ROW DECODER
I/O2
SENSE AMPS 1024 x 32 x 8 ARRAY
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
I/O3 I/O4 I/O5
COLUMN DECODER
POWER DOWN
I/O6 I/O7
OE A1 A2 A3 A4 WE V CC A5 A6 A7 A8 A9 A 10 A 11
TSOP I Top View (not to scale)
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A0 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 14 A 13 A 12
A 10
A 12 A 13
A 11
Selection Guide
7C199 -8 8 120 L Maximum CMOS Standby Current L
Shaded area contains advance information.
A 14
Maximum Access Time Maximum Operating Current
0.5
7C199 -10 10 110 90 0.5 0.05
7C199 -12 12 160 90 10 0.05
7C199 -15 15 155 90 10 0.05
7C199 -20 20 150 90 10 0.05
7C199 -25 25 150 80 10 0.05
7C199 -35 35 140 70 10 0.05
7C199 -45 45 140 10
Unit ns mA mA
Cypress Semiconductor Corporation Document #: 38-05160 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 7, 2003
CY7C199
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... -0.5V to +7.0V DC Voltage Applied to Outputs in High-Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] .................................-0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Military Ambient Temperature[2] 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range (-8, -10, -12, -15)[3]
7C199-8 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l L Mil 5 5 5 0.5 0.05 0.5 0.05 30 5 10 0.05 Test Conditions VCC = Min., IOH=-4.0 mA VCC = Min., IOL=8.0 mA 2.2 -0.5 -5 -5 2.4 0.4 VCC +0.3V 0.8 +5 +5 120 2.2 -0.5 -5 -5 7C199-10 2.4 0.4 VCC +0.3V 0.8 +5 +5 110 85 2.2 -0.5 -5 -5 7C199-12 2.4 0.4 VCC +0.3V 0.8 +5 +5 160 85 2.2 -0.5 -5 -5 7C199-15 2.4 0.4 VCC +0.3V 0.8 +5 +5 155 100 180 30 5 10 0.05 15
[3]
Min. Max. Min. Max. Min. Max. Min. Max. Unit V V V V A A mA mA mA mA mA mA mA mA
ISB1
Automatic CE Power-down Current-- TTL Inputs Automatic CE Power-down Current-- CMOS Inputs
Max. VCC, CE > Com'l VIH, VIN > VIH or L VIN < VIL, f = fMAX Max. VCC, Com'l CE > VCC - 0.3V L VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Mil
ISB2
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45)
7C199-20 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l L Mil Test Conditions VCC = Min., IOL = 8.0 mA 2.2 -0.5 -5 -5 VCC = Min., IOH = -4.0 mA 2.4 0.4
7C199-25 2.4 0.4
7C199-35 2.4 0.4 2.2 -0.5 -5 -5 VCC +0.3V 0.8 +5 +5 140 70 150
7C199-45 Min. 2.4 0.4 2.2 -0.5 -5 -5 VCC +0.3V 0.8 +5 +5 140 70 150 Max. Unit V V V V A A mA mA mA
Min. Max. Min. Max. Min. Max.
VCC 2.2 VCC +0.3V +0.3V 0.8 +5 +5 150 90 170 -0.5 -5 -5 0.8 +5 +5 150 80 150
Shaded area contains advance information. Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "instant on" case temperature. 3. See the last page of this specification for Group A subgroup testing information.
Document #: 38-05160 Rev. *A
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CY7C199
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45) (continued)[3]
7C199-20 Parameter ISB1 Description Automatic CE Power-down Current-- TTL Inputs Automatic CE Power-down Current-- CMOS Inputs Test Conditions Max. VCC, CE > VIH, Com'l VIN > VIH or VIN < VIL, L f = fMAX Max. VCC, Com'l CE > VCC - 0.3V L VIN > VCC - 0.3V or Mil VIN < 0.3V, f=0 30 5 10 0.05 15 7C199-25 30 5 10 0.05 15 7C199-35 25 5 10 0.05 15 7C199-45 Min. Max. Unit 25 5 10 0.05 15 mA mA mA A mA Min. Max. Min. Max. Min. Max.
ISB2
Capacitance[4 ]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
AC Test Loads and Waveforms[5]
R1 481 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: R2 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 167 OUTPUT 1.73V R2 255 3.0V 10% GND R1 481 ALL INPUT PULSES 90% 90% 10%
tr
tr
(a)
(b)
THEVENIN EQUIVALENT
Data Retention Characteristics Over the Operating Range (L-version only)
Parameter VDR ICCDR tCDR[4] tR [5] Description VCC for Data Retention Data Retention Current Com'l Com'l L Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 200 Conditions[6] Min. 2.0 Max. Unit V A 10 A ns s
Data Retention Waveform
DATA RETENTION MODE VCC 3.0V tCDR CE
Note: 4. Tested initially and after any design or process changes that may affect these parameters. 5. tR< 3 ns for the -12 and the -15 speeds. tR< 5 ns for the -20 and slower speeds 6. No input may exceed VCC + 0.5V.
VDR > 2V
3.0V tR
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CY7C199
Switching Characteristics Over the Operating Range (-8, -10, -12, -15)
7C199-8 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to High-Z CE HIGH to
[8, 9] [3, 7]
7C199-10 Min. 10 Max.
7C199-12 Min. 12 Max.
7C199-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 15 10 10 0 0 9 9 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 3 ns ns
Description
Min. 8
Max.
8 3 8 4.5 0 5 3 4 0 8 8 7 7 0 0 7 5 0 5 3 3 10 7 7 0 0 7 5 0 0 3 0 3
10 3 10 5 0 5 3 5 0 10 12 9 9 0 0 8 8 0 6 3
12 12 5 5 5 12
CE LOW to Low-Z[8] High-Z[8,9] CE LOW to Power-up CE HIGH to Power-down Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9] WE HIGH to Low-Z[8]
Write Cycle[10, 11]
7
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to CE HIGH to High-Z[8, 9] 3 9 0 0 High-Z[8, 9] CE LOW to Low-Z[8] CE LOW to Power-up 0 9 3 11 0 3 20 9 0 11 3 15 0 20 20 3 25 10 0 15 3 15 25 25 3 35 16 0 15 35 35 3 45 16 45 45 ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C199-25 Min. Max. 7C199-35 Min. Max. 7C199-45 Min. Max. Unit
Shaded area contains advance information. Notes: 7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C199
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20 Parameter tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle[10,11] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9] 3 WE HIGH to Low-Z[8] 20 15 15 0 0 15 10 0 10 3 25 18 20 0 0 18 10 0 11 3 35 22 30 0 0 22 15 0 15 3 45 22 40 0 0 22 15 0 15 ns ns ns ns ns ns ns ns ns ns Description CE HIGH to Power-down Min. Max. 20 7C199-25 Min. Max. 20 7C199-35 Min. Max. 20 7C199-45 Min. Max. 25 Unit ns
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 [13, 14]
CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tPD ICC 50% ISB tHZOE tHZCE DATA VALID tRC
HIGH IMPEDANCE
DATA OUT
Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW.
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CY7C199
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
OE tSD DATA I/O tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC ADDRESS CE tSA tAW tHA tSCE
WE tSD DATA I/O DATA IN VALID tHD
Write Cycle No. 3 (WE Controlled OE LOW)[11, 16]
tWC ADDRESS
CE tAW WE tSA tHA
tSD DATA I/O tHZWE
Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
tHD
DATAIN VALID tLZWE
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CY7C199
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC,I SB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN =5.0V TA =25C ICC NORMALIZED ICC,I SB 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -55 ISB 25 125 VCC =5.0V VIN =5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC =5.0V TA =25C
SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED t AA 1.3 NORMALIZED t AA 1.2 1.1 TA =25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT (mA) 140 120 100 80 60 40 20 0 0.0
OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V 0.8 0.6 -55
VCC =5.0V TA =25C
25
125
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 NORMALIZED I PO DELTA t AA (ns) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0
AMBIENT TEMPERATURE (C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED I CC
OUTPUT VOLTAGE (V)
NORMALIZED I CC vs. CYCLE TIME
25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 VCC =4.5V TA =25C
1.00
VCC =5.0V TA =25C VIN =0.5V
0.75
0.50 10
20
30
40
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output disabled Mode Deselect/Power-down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Page 7 of 13
Document #: 38-05160 Rev. *A
CY7C199
Ordering Information
Speed (ns) 8 Ordering Code CY7C199-8VC CY7C199-8ZC CY7C199L-8VC CY7C199L-8ZC CY7C199-10VC CY7C199-10ZC CY7C199L-10VC CY7C199L-10ZC CY7C199-10VI CY7C199-10ZI CY7C199L-10VI CY7C199L-10ZI CY7C199-12PC CY7C199-12VC CY7C199-12ZC CY7C199L-12PC CY7C199L-12VC CY7C199L-12ZC CY7C199-12VI CY7C199-12ZI CY7C199L-12VI CY7C199L-12ZI CY7C199-15PC CY7C199-15VC CY7C199-15ZC CY7C199L-15PC CY7C199L-15VC CY7C199L-15ZC CY7C199-15VI CY7C199-15ZI CY7C199-15DMB CY7C199-15LMB CY7C199L-15DMB CY7C199L-15LMB CY7C199-20PC CY7C199-20VC CY7C199-20ZC CY7C199L-20PC CY7C199L-20VC CY7C199L-20ZC CY7C199-20VI CY7C199-20ZI CY7C199-20DMB CY7C199-20LMB CY7C199L-20DMB CY7C199L-20LMB Package Name V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 V21 Z28 P21 V21 Z28 P21 V21 Z28 V21 Z28 V21 Z28 P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 P21 V21 Z28 P21 V21 Z28 V21 Z28 D22 L54 D22 L54 Package Type 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier Operating Range Commercial
10
Commercial
Industrial
12
Commercial
Industrial
15
Commercial
Industrial Military
20
Commercial
Industrial Military
Shaded area contains advance information. Contact your Cypress sales representative for availability
Document #: 38-05160 Rev. *A
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CY7C199
Ordering Information (continued)
Speed (ns) 25 Ordering Code CY7C199-25PC CY7C199-25SC CY7C199-25VC CY7C199-25ZC CY7C199-25SI CY7C199-25VI CY7C199-25ZI CY7C199-25DMB CY7C199-25LMB CY7C199-35PC CY7C199-35SC CY7C199-35VC CY7C199-35ZC CY7C199-35SI CY7C199-35VI CY7C199-35ZI CY7C199-35DMB CY7C199-35LMB CY7C199-45DMB CY7C199-45LMB Package Name P21 S21 V21 Z28 S21 V21 Z28 D22 L54 P21 S21 V21 Z28 S21 V21 Z28 D22 L54 D22 L54 Package Type 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Thin Small Outline Package 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier 28-Lead (300-Mil) CerDIP 28-Pin Rectangular Leadless Chip Carrier Operating Range Commercial
Industrial
Military Commercial
35
Industrial
Military Military
45
Shaded area contains advance information. Contact your Cypress sales representative for availability
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter Read Cycle tRC tAA tOHA tACE tDOE Write Cycle tWC tAA tAW tHA tSA tPWE tSD tHD Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
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CY7C199
Package Diagrams
28-pin (300-Mil) CerDIP D22
MIL-STD-1835 D-15 Config. A
51-80032-**
28-pin Rectangular Leadless Chip Carrier L54
MIL-STD-1835 C-11A
51-80067-**
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CY7C199
Package Diagrams (continued)
28-pin (300-Mil) Molded DIP P21
51-85014-B
28-pin
(300-Mil) Molded SOIC S21
51-85026-A
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CY7C199
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ V21
51-85031-B
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05160 Rev. *A Page 12 of 13
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C199
Document History Page
Document Title: CY7C199 32K x 8 Static RAM Document Number: 38-05160 REV. ** *A ECN NO. 109971 121730 Issue Date 10/28/01 01/09/02 Orig. of Change SZV DFP Description of Change Change from Spec number: 38-00239 to 38-05160 Updated Product Offering table.
Document #: 38-05160 Rev. *A
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